1. Field of the Invention
The present invention relates to a circuit design, and more particularly, to a digital circuit design method and associated computer program product.
2. Description of the Prior Art
Traditional digital circuit design is mainly categorized into front-end stage and back-end stage, wherein the front-end stage mainly comprises Register Transfer Level (RTL) design, functional simulation and logic synthesis, and the back-end stage comprises physical design, automatic placement and routing, and post-layout simulation, etc.
In general, after the logic synthesis but before the physical design, the functional simulation with the timing delay information is not needed, besides doing this kind of simulation is difficult. For example, in the setting of the logic synthesis, high fan-out nets of the circuit will be annotated with huge delay times in the timing information generated by the logic synthesis, so the netlist generated can't be simulated with the timing information given by the logic synthesis.
The above-mentioned high fan-out net requires extra processes in the following physical design to make the delay time short. However, since the post-layout simulation, executed after the physical design, usually is pretty close to tape out, if the problems are discovered in post-layout simulation, the product schedule may be affected.
For digital design, if the constraint applied in the logic synthesis is correct and sufficient in its coverage, and a correct static timing analysis (STA) is performed accordingly to passes the verification, the post-layout simulation might not have error generally. However, sometimes engineers make mistakes in designing the timing constraints so that the static timing analysis is performed with a timing-loosening constraint and that the errors can not be discovered until the post-layout simulation. Some circuits even can not be checked with static timing analysis, in which case, with current design flow, the error can possibly be discovered only in the post-layout simulation. However, as the abovementioned statements, it's usually too late if this kind of error is discovered after the physical design.